A molded flip-chip semiconductor package is comprised of a semiconductor chip electrically connected to a surface of a substrate via a plurality of solder bumps mounted on an active surface of the semiconductor chip, an encapsulant formed on the surface of the substrate by a molding process to encapsulate the semiconductor chip, and a plurality of solder balls implanted on an opposite surface of the substrate and serving as I/O terminals for electrically connecting the semiconductor chip to an external device. Such package design greatly reduces the size of the package, such that the semiconductor chip and the substrate can be made comparable in size. The flip-chip design also eliminates the use of conventional bonding wires, thereby desirably reducing impedance and enhancing electrical performance of the package. Accordingly, the flip-chip package represents a mainstream packaging technology nowadays. The related prior arts include U.S. Pat. No. 6,038,136, U.S. Pat. No. 6,867,487, and Taiwanese Patent No. 1244145.
With a semiconductor chip becoming larger (greater than 15 mm×15 mm), due to mismatch in coefficient of thermal expansion (CTE) between the semiconductor chip and the encapsulant and also a large contact area therebetween, both the thermal stress and thermal deformation arising during the thermal cycle of chip packaging are directly proportional to a corner-to-center distance of the semiconductor chip, that is, δ (deformation)=α (coefficient of thermal expansion)×L (a distance from a location where deformation=0)×Δt (amount of temperature variation). In particular, corners of a flip-chip semiconductor chip 10 (as shown in FIG. 1) are located farthest from the center of the chip 10 (where deformation=0) and thereby are subjected to the greatest thermal stress and thermal deformation. As a result, delamination usually occurs at the corners of the semiconductor chip and adversely affects the product quality.
To solve the delamination problem, U.S. Pat. Nos. 5,773,362, 6,184,064 and 6,225,695 disclose roughening a non-active surface of a semiconductor chip to thereby reinforce the bonding between the semiconductor chip and an encapsulant that encapsulates the semiconductor chip.
Referring to FIG. 1, which is a cross-sectional view of a conventional molded flip-chip semiconductor package, a semiconductor chip 10 is electrically connected to a substrate 12 via a plurality of solder bumps 11 mounted on an active surface 101 of the semiconductor chip 10, and a roughened structure 100 is formed on the entire non-active surface 102 of the semiconductor chip 10, such that the bonding between the semiconductor chip 10 and an encapsulant 13 formed on the substrate 12 can be enhanced by the roughened structure 100, thereby reducing delamination between the semiconductor chip 10 and the encapsulant 13.
However, roughening the surface of the semiconductor chip decreases the surface strength of the semiconductor chip. For a semiconductor chip to be used in a compact package for a miniaturized electronic product, the semiconductor chip must be thinned, and roughening a non-active surface of such thinned semiconductor chip would greatly reduce the structural strength of the semiconductor chip and thereby lead to cracks of the semiconductor chip. This situation becomes more severe for a thin and large semiconductor chip.
Therefore, the problem to be solved here is to provide a semiconductor package suitable for a large semiconductor chip, which can prevent delamination on the corners of the semiconductor chip, reduction in the structural strength of the semiconductor chip, and cracks of the semiconductor chip.